1. Field of the Invention
This invention relates generally to integrated circuit devices, and more particularly to integrated circuit devices employing antifuses.
2. Background of the Technical Art
The manufacture of integrated circuit (IC) devices includes the formation of metallization layers that are patterned to create interconnections between devices. Some IC interconnections are programmable, either with fuses or antifuses. An un-programmed fuse is a low-resistance link between or within metallization layers which can be "programmed" by being "blown", i.e. it can be caused to become non-conductive by applying a high enough current across it to "blow." Antifuses operate in an opposite fashion to standard fuses in that the "un-programmed" material used to form the antifuse has an intrinsically high resistance, and the programmed material has a relatively low resistance. By applying a programming current of about 10 milli-Amperes (mA), the electrical resistance through the anti-fuse material is greatly reduced, thus providing a conductive link between or within metallization layers. A typical material used in antifuses is amorphous silicon (A-Si) which has an intrinsic (un-programmed) resistivity of over 1 giga-ohm-cm.
A prior art antifuse structure is shown in cross-section in FIG. 1. A substrate 12 typically comprises a semiconductor wafer, such as a silicon wafer. An oxide layer 14 overlays the substrate 12, and can be formed by a variety of well-known processes such as chemical vapor deposition (CVD). A metal layer 16 is formed over the oxide layer, typically by a physical vapor deposition (PVD) process such as aluminum sputtering. The metal layer 16 is covered by a second oxide layer 18 which has a via formed through it by standard masking and etching techniques that are well known to those skilled in the art. An antifuse material (such as A-Si) can then be deposited in the via 20 to form an antifuse structure 22. The antifuse material is typically deposited by blanket deposition and etch-back to fill the via. A metal layer 24 (usually aluminum or an aluminum alloy) is then formed over the oxide layer 18 and the antifuse structure 22, again typically by a PVD process. In an actual process, barrier layers such as barrier metal layers made from TiW preferably separate the A-Si from the aluminum metal layers to minimize A-Si degrading alloy-type interactions. This can be accomplished by providing a thin film of the barrier layer on top of metal layer 16 and on the bottom of metal layer 24.
Programming of the antifuse structure 22 is accomplished by providing a current of about 10 mA between metal layer 16 and the metal layer 24. Before programming, the antifuse structure 22 has a resistance of above 1 giga-ohms for a 1 micron diameter via 20. A programmed antifuse forms a conductive path 26 between metal layers 16 and 24 having a resistance typically of about 20-100 ohms.
Antifuse structures allow for much higher programmable interconnection densities than standard fuse structures. However, anti fuse structures exhibit a relatively high programmed resistance, which can be problematical in some applications. Actel Corporation describes their solution to this problem in "An FPGA Family Optimized for High Densities and Reduced Routing Delay", Ahrens et al, IEEE 1990 Custom Integrated Circuits Conference, 1990. This article presents a method for arranging antifuses in a single layer and coupling them in parallel to reduce their resistance. While the Actel solution reduces the programmed resistance problem, it also reduces the antifuse density on the integrated circuit.